/*
 * nau88c22.h  --  NAU88C22 Soc Audio Codec driver
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __NAU88C22_H__
#define __NAU88C22_H__

#define SLAVE_ADDR 0x1a 

#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))


/*
 * Register values.
 */
#define NAU88C22_RESET				0x00
#define NAU88C22_POWER_MANAGEMENT_1		0x01
#define NAU88C22_POWER_MANAGEMENT_2		0x02
#define NAU88C22_POWER_MANAGEMENT_3		0x03
#define NAU88C22_AUDIO_INTERFACE		0x04
#define NAU88C22_COMPANDING_CONTROL		0x05
#define NAU88C22_CLOCKING			0x06
#define NAU88C22_ADDITIONAL_CONTROL		0x07
#define NAU88C22_GPIO_CONTROL			0x08
#define NAU88C22_JACK_DETECT_CONTROL_1		0x09
#define NAU88C22_DAC_CONTROL			0x0A
#define NAU88C22_LEFT_DAC_DIGITAL_VOLUME	0x0B
#define NAU88C22_RIGHT_DAC_DIGITAL_VOLUME	0x0C
#define NAU88C22_JACK_DETECT_CONTROL_2		0x0D
#define NAU88C22_ADC_CONTROL			0x0E
#define NAU88C22_LEFT_ADC_DIGITAL_VOLUME	0x0F
#define NAU88C22_RIGHT_ADC_DIGITAL_VOLUME	0x10
#define NAU88C22_EQ1				0x12
#define NAU88C22_EQ2				0x13
#define NAU88C22_EQ3				0x14
#define NAU88C22_EQ4				0x15
#define NAU88C22_EQ5				0x16
#define NAU88C22_DAC_LIMITER_1			0x18
#define NAU88C22_DAC_LIMITER_2			0x19
#define NAU88C22_NOTCH_FILTER_1			0x1B
#define NAU88C22_NOTCH_FILTER_2			0x1C
#define NAU88C22_NOTCH_FILTER_3			0x1D
#define NAU88C22_NOTCH_FILTER_4			0x1E
#define NAU88C22_ALC_CONTROL_1			0x20
#define NAU88C22_ALC_CONTROL_2			0x21
#define NAU88C22_ALC_CONTROL_3			0x22
#define NAU88C22_NOISE_GATE			0x23
#define NAU88C22_PLL_N				0x24
#define NAU88C22_PLL_K1				0x25
#define NAU88C22_PLL_K2				0x26
#define NAU88C22_PLL_K3				0x27
#define NAU88C22_3D_CONTROL			0x29
#define NAU88C22_BEEP_CONTROL			0x2B
#define NAU88C22_INPUT_CONTROL			0x2C
#define NAU88C22_LEFT_INP_PGA_CONTROL		0x2D
#define NAU88C22_RIGHT_INP_PGA_CONTROL		0x2E
#define NAU88C22_LEFT_ADC_BOOST_CONTROL		0x2F
#define NAU88C22_RIGHT_ADC_BOOST_CONTROL	0x30
#define NAU88C22_OUTPUT_CONTROL			0x31
#define NAU88C22_LEFT_MIXER_CONTROL		0x32
#define NAU88C22_RIGHT_MIXER_CONTROL		0x33
#define NAU88C22_LOUT1_HP_CONTROL		0x34
#define NAU88C22_ROUT1_HP_CONTROL		0x35
#define NAU88C22_LOUT2_SPK_CONTROL		0x36
#define NAU88C22_ROUT2_SPK_CONTROL		0x37
#define NAU88C22_OUT3_MIXER_CONTROL		0x38
#define NAU88C22_OUT4_MIXER_CONTROL		0x39
#define NAU88C22_POWER_MANAGEMENT_4		0x3A
#define NAU88C22_LEFT_TIMESLOT			0x3B
#define NAU88C22_MISC				0x3C
#define NAU88C22_RIGHT_TIMESLOT			0x3D
#define NAU88C22_DEV_REVISION			0x3E
#define NAU88C22_DEVICEID			0x3F
#define NAU88C22_DAC_DITHER			0x41
#define NAU88C22_ALC_ENHANCE_1			0x46
#define NAU88C22_ALC_ENHANCE_2			0x47
#define NAU88C22_192KHZ_SAMPLING		0x48
#define NAU88C22_MISC_CONTROL			0x49
#define NAU88C22_INPUT_TIEOFF			0x4A
#define NAU88C22_POWER_REDUCTION		0x4B
#define NAU88C22_AGC_PEAK2PEAK			0x4C
#define NAU88C22_AGC_PEAK_DETECT		0x4D
#define NAU88C22_AUTOMUTE_CONTROL		0x4E
#define NAU88C22_OUTPUT_TIEOFF			0x4F

#define NAU88C22_MAX_REGISTER			0x4F

#define NAU88C22_CACHEREGNUM			79

/* Clock divider Id's */
enum nau88c22_clk_id {
	NAU88C22_OPCLKRATE,
	NAU88C22_BCLKDIV,
};

enum nau88c22_sysclk_src {
        NAU88C22_MCLK,
	NAU88C22_PLL
};

extern void nau88c22_init(void);

#endif	/* __NAU88C22_H__ */
